Counter simulation

Thanks for the Info. I just tried with the gray coded counter. (The code is given below). Even this case, there are glitches. This has surprised me since only one line should change in this case. For example, from six->four, transitional values of 4 and 5 are noted. Has this to something to do with capacitances...etc? (Also attached is the image).

Please also note that the timing delays before the state change. Is that because I got the I/O ports of the module left unassigned to real pins of the FPGA (I am using cyclone II 2c35 as my test device).

Thanks.

Here is my code:

module test(clk, reset, tstport);

input clk,reset;

output [2:0] tstport;

reg [2:0] cnt;

assign tstport=cnt;

always @(posedge clk or negedge reset)

begin

if(reset==1'b0) begin cnt<=3'b000; end

else

begin

case(cnt)

3'b000: cnt<=3'b001;

3'b001: cnt<=3'b011;

3'b011: cnt<=3'b010;

3'b010: cnt<=3'b110;

3'b110: cnt<=3'b100;

3'b100: cnt<=3'b000;

3'b101: cnt<=3'b000;

3'b111: cnt<=3'b000;

default: cnt<=3'b000;

endcase

end

end

endmodule