Counter simulation

You didn't examine the simulation results thoroughly. Take a look at the individual output bits, then you see, that they always have a correct logic state according to the expected counter value, there are no glitches! The problem is however, that they don't change state exactly at the same time, cause each output has an individual delay.

Quartus performs timing rather than functional simulation by default and takes routing delay into account.

As general problem behind the simulation, a binary coded value isn't valid without a clock or a qualifier, that guarantees the value isn't just changing when you watch it. You would need a gray coded counter to overcome this problem.

Just an additional remark regarding coding style. Although the used blocking assignment is correct Verilog syntax,

cnt=cnt+3'b001; //useful $0-$5 (needed only six states)
if(cnt>3'b101) cnt=3'b000; 

I would prefer non-blocking assignment to avaoid potentially confusing multiple assignments to cnt.

if(cnt>=5) cnt<=3'b000;
else cnt<=cnt+3'b001;