Counter Problems

Your code is too nested and complicated...

 
signal count : signed(32 downto 0);
signal temp : signed(1 downto 0);
 
process(reset,clk)
begin
if reset = '1' then
    in_signal_d <= '0';
    temp <= "00";
    count <= (others => '0');
elsif rising_edge(clk) then
 
   in_signal_d <= in_signal;  -- your incoming signal
 
   if count_up = '1' then
        temp <= "01";        --   +1
   else
       temp <= "11";         --   -1
   end if;
 
   if in_signal /= in_signal_d then   -- either edge
      count <= count + temp;
   end if;
 
end if;
end process;
 
cnt <= std_logic_vector(count);