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Altera_Forum
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8 years ago

Could the refclk_1 of Cyclone IV GX (EP4CGX50CF23I7) be input refclk of transceiver?

Hi, all: I'm using Cyclone IV GX (EP4CGX50CF23I7) to design some SerDes project. When I assign the refclk_1 pin (BANK 3B, REFCLK_1 , M8、N8) to the pll_clkin of transceiver, it can'...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Agreed. On the face of it you should be able to feed that PLL from that clock pin. So, I suggest you have another conflicting constraint that's causing the problem.

Can you realise a fit by removing all other constraints and leaving only the clock pin assignment?

Cheers,

Alex