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Honored Contributor
Honored ContributorCould the refclk_1 of Cyclone IV GX (EP4CGX50CF23I7) be input refclk of transceiver?
Hi, all: I'm using Cyclone IV GX (EP4CGX50CF23I7) to design some SerDes project. When I assign the refclk_1 pin (BANK 3B, REFCLK_1 , M8、N8) to the pll_clkin of transceiver, it can'...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- There are restrictions regarding which clock pins connect to which PLLs. Refer to Figure 5-9 on page 5-20 of the "cyclone iv device handbook (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-5v1.pdf)". See note (1) Refer to the specific device pinouts for the location of these clock pins. Cheers, Alex --- Quote End --- Thanks for your answer. But Figure 5-9 is PLL internal block diagram, and it refers that the clock source can come from any of the four clock pins located on the same side as the PLL. According to Figure 5-3 of the same handbook, refclk_1 should be used as input clock of PLL_5. But when I placed the pin as input clock, the compilation was unsuccessful. https://alteraforum.com/forum/attachment.php?attachmentid=13449&stc=1
