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Altera_Forum
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8 years ago

Could the refclk_1 of Cyclone IV GX (EP4CGX50CF23I7) be input refclk of transceiver?

Hi, all: I'm using Cyclone IV GX (EP4CGX50CF23I7) to design some SerDes project. When I assign the refclk_1 pin (BANK 3B, REFCLK_1 , M8、N8) to the pll_clkin of transceiver, it can'...
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Altera_Forum
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8 years ago

There are restrictions regarding which clock pins connect to which PLLs. Refer to Figure 5-9 on page 5-20 of the "cyclone iv device handbook (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-5v1.pdf)". See note (1)

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Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.

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Refer to the specific device pinouts for the location of these clock pins.

Cheers,

Alex