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The VHDL code is trying to use a component compiled into the rtl_work library. You can either compile your code into rtl_work via;
vsim> vlib rtl_work
vsim> vmap rtl_work [pwd]/rtl_work
vsim> vcom -work rtl_work <your VHDL files>
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Hello,
by typing this, how do you fill
<your vhdl files>, by typing my vhdl files root (
C:\Users\Alfonso\Desktop\PFC\altera) returns this:
(I typed vsim> vcom -work rtl_work
C:\Users\Alfonso\Desktop\PFC\altera) # Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011# ** Error: (vcom-7) Failed to open design unit file "C:UsersAlfonsoDesktopPFCltera" in read mode.# Invalid argument. (errno = EINVAL)# E:/altera/11.1sp2/modelsim_ase/win32aloem/vcom failed.
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or you can simply map the rtl_work library to the same location as the work directory, eg., assuming you have created your work directory in the same folder you are working in via
vsim> vlib work
vsim> vmap work [pwd]/work
then you can tell Modelsim to look in the work directory for the rtl_work components too by mapping it via
vsim> vmap rtl_work [pwd]/work
(You don't need the [pwd] statement if you don't want to use absolute paths in your .ini or .mpf file).
Cheers,
Dave
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It did not work, assuming [pwd] is written as [pwd] litterally (if it is a root instead, tell me) after typing those three lines literally as you did it continues returning me:
# ** Error: (vsim-3170) Could not find '
C:\Users\Alfonso\Desktop\PFC\simulation\modelsim\rtl_work.TB_PFC_main'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./PFC_run_msim_rtl_vhdl.do PAUSED at line 34
Please help me i cannot test my code till this is solved.
Honored Contributor
