Could a dual clock dual input DFF be implemented in FPGA?

Actually, I think the problem is too isolated. What are you doing after capturing the data? You can't use both clk1 and clk2 simultaneously throughout your design(there is no such thing as a dual-edge register), so you're going to have to settle on clk1, clk2, or a third clock not yet described. If you settle on clk1, then it's only going to be able to take in half the data. Same as clk2. The other option is to keep the data as two parallel lanes, i.e. d1 and d2. If that's the case, you can then synchronize them both back to your system clock domain(clk1, clk2 or other) and use them that way.