Cordic Processor descreption VHDL

it is the cordic processor descreption with a pipline cellul, I need the VHDL descreption of package "constantes_cordic.all"

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description du processeur

cordic à accumulateur

b.1 cellule du pipeline

-- description d’une cellule du pipeline

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use work.constantes_cordic.all;

entity cordic_cell is

generic (resolution : natural := out_n;

cell_id : natural := 1

);

port (clk, rst : in std_logic;

-- les ’signed’ sont représentés en

-- complément à 2

X1 : in signed(resolution-1 downto 0);

Y1 : in signed(resolution-1 downto 0);

Z1 : in signed(resolution-1 downto 0);

X2 : out signed(resolution-1 downto 0);

Y2 : out signed(resolution-1 downto 0);

Z2 : out signed(resolution-1 downto 0)

);

end entity cordic_cell;

architecture arch_cordic_cell of cordic_cell is

signal X2_t,Y2_t,Z2_t,X1_s,Y1_s,atan :

signed(resolution-1 downto 0);

signal Z_sign : std_logic;

-- fonction décalage à droite arithmétique

-- d’amplitude n ( sur entier en complément à 2)

function rshift(val : in signed) return signed is

variable tampon : signed(val’range);

begin

for i in val’high downto val’high-cell_id+1 loop

-- on place à 0 (nbr positif) ou 1 (nbr négatif)

-- les n msbs

tampon(i):= val(val’range);

end loop;

for i in val’range-cell_id downto 0 loop

-- on décale vers la droite le reste des

-- bits

tampon(i):= val(i+cell_id);

end loop;

return tampon;

end function rshift;

-- fonction addition / soustraction

function addsub(v1 : in signed;

v2 : in signed;

sign : in std_logic)

return signed is

begin

if sign = ’1’ then

return v1+v2;

else

return v1-v2;

end if;

end function addsub;

begin

Z_sign <= Z1(resolution-1);

atan <= arctan(cell_id);

X1_s <= rshift(X1);

Y1_s <= rshift(Y1);

X2_t <= addsub(X1,Y1_s,Z_sign);

Y2_t <= addsub(Y1,X1_s,not Z_sign);

Z2_t <= addsub(Z1,atan,Z_sign);

cordic_process : process(rst,clk)

begin

if rst=’1’ then

X2 <= (others=>’0’);

Y2 <= (others=>’0’);

Z2 <= (others=>’0’);

elsif rising_edge(clk) then

X2 <= X2_t;

Y2 <= Y2_t;

Z2 <= Z2_t;

end if;

end process cordic_process;

end arch_cordic_cell;

B.2 pipeline

-- description du pipeline

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use work.constantes_cordic.all;

entity cordic is

port (clk, rst : in std_logic;

theta : in signed(out_n-1 downto 0);

rho_2 : in signed(out_n-1 downto 0);

cos : out signed(out_n-1 downto 0);

sin : out signed(out_n-1 downto 0)

);

end entity cordic;

architecture pipeline_simple of cordic is

-- signaux de connexion entre les différentes

-- cellules du pipeline

signal X,Y,Z : pipeline_array;

-- cellule de pipeline

component cordic_cell is

generic (resolution : natural := out_n;

cell_id : natural := 1

);

port (clk, rst : in std_logic;

X1 : in signed(resolution-1 downto 0);

Y1 : in signed(resolution-1 downto 0);

Z1 : in signed(resolution-1 downto 0);

X2 : out signed(resolution-1 downto 0);

Y2 : out signed(resolution-1 downto 0);

Z2 : out signed(resolution-1 downto 0)

);

end component cordic_cell;

begin

-- correspondance des signaux

X(0) <= rho_2;

Y(0) <= (others => ’0’);

Z(0) <= theta;

cos <= X(pipeline_n);

sin <= Y(pipeline_n);

fabrication_pipeline :

for n in 1 to pipeline_n generate

pipe_cell : cordic_cell

generic map (resolution => out_n,

cell_id => n)

port map (clk => clk,

rst => rst,

X1 => X(n-1),

Y1 => Y(n-1),

Z1 => Z(n-1),

X2 => X(n),

Y2 => Y(n),

Z2 => Z(n));

end generate fabrication_pipeline;

end pipeline_simple;