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Altera_Forum
Honored Contributor
Honored ContributorConverting Behavioral to Gate Level
I want to convert my behavioral VHDL description to its gate level one. How can I do this using Quartus II? Regards http://www.alteraforum.com/forum//proweb/misc/progress.gif
Altera_ForumHonored Contributor
Honored ContributorIf you are using the Quartus native simulator, just run a timing simulation instead of a functional simulation.
If you are using a third-party simulator, you can start with Quartus on-line help. On the help Contents tab, go to "Integrating Other EDA Tools --> Specifying EDA Tool Settings". This page tells you how to generate the .vho or .vo gate-level netlist with Quartus. On the help Contents tab, go to "Integrating Other EDA Tools --> Using Other EDA Simulation Tools --> About Using the <third-party> Software with the Quartus II Software --> Performing a Timing Simulation with the <third party> Software".
