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Simple question, lots of answers.
The most straighforward way is to generate a 1Hz clock by using a counter: toggle the 1Hz clock every 25_000_000 cycles of the 50Mhz clock.
A couple of issues.
First, this will require a 23 bit counter running at 50 Mhz. You can use a PLL to generate a 100 kHz clock (PLLs have lower limits) and then use a counter to generate the 1 Hz clock from the 100 kHz clock.
Also, at a 1 Hz it's not really a problem but ripple clocks are best avoided and replaced by clock enables.
reg [9:0] counter;
reg enable;
always @ (posedge clk100k)
begin
if (counter == 10'd0) counter <= 10'd100_000;
else counter <= counter - 1'd1;
enable <= counter == 10'd0;
end
always @ (posedge clk100k)
begin
if (enable) begin
// your logic here is run only once every second
end
end
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I was wondering if the following codes gonna work if I feed the clock input to the 50MHz clock. I ran a simulation on this code (I dont have the Altera board at home) and the report shows the code works.
Please suggest...
module Lab6a(clock, reset, cout);
input clock, reset;
output cout;
reg count; //counts upto 50000000
reg cout; //original 4 bit counter
always @ (posedge clock)
begin
if (~reset) begin
if(count==50000000) begin
count <= 0;
cout = cout + 1;
end else begin
count <= count + 1;
cout <= cout;
end
end else begin
count <=0;
cout <= 0;
end
end
endmodule
Thanks Again!!!
Honored Contributor
