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The current code has many unclocked dividers between registers that will limit your max clock speed to something very slow.
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That's true, but considering the design purpose, it could run at kHz clock speed without problems. The basic problem is the large amount of wide dividers. But if the design is intended to learn HDL programming, then pipelined dividers shoul be used.
An addional problem is created by using unrestricted integer type for most signals. The design compilers isn't able to recognize the actual needed number ranges.
Generally, the design style suggests a lack of understanding how hardware logic works. It would be interesting challenge to find an FPGA adequate coding of the present problem. But I wonder, if it's more reasonable to start with a more simple arithemetic problems.
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