Honored Contributor
Honored ContributorA "LE" is a logic element. Different devices have different numbers of them.
Basically, this is going to need a complete re-design. You will have to cope with limited numbers of dividers, maybe 2 or 3 , rather than the 20 or so you have in your design. Each divider should also have a latency of several clock cycles, rather than the asynchronous versions that are implemented in your code (interestingly, Timequest crashes while trying to assess your design!). The current code has many unclocked dividers between registers that will limit your max clock speed to something very slow. My Recommendation would be to start from scratch. Think about the design logic and draw it all out before you write any VHDL.
