Conversion uses all combinational logic

To understand about the problems involved by your design, you can do like this:

Compile the design without a particular FPGA selected. e.g. Cyclone III, auto device selection. Then browse the Resource Utilization by Entity category in Compilation report/Analysis and synthesis.

You'll notice, that most of the 18k LEs is consumed by the various large dividers in your design (including mod operations, which also uses dividers). Parallel dividers have a huge resource utilzation and should be avoided, if possible.

This is a kind of design that's not well suited for FPGA implementation. There are surely options to reduce the resource usage. Implementing slow serial dividers would be an obvious one.