conversion of std_logic (NOT std_logic_vector) to integer

I just thought Id show off a little bit, just to show you the things you can do with VHDL. There is nothing forcing you to using integers for arrays. You can actually use any enumerated type. eg:

type sl_array_t is array( std_logic range <> ) of integer;
signal my_array : sl_array('0' to '1');
signal sel : std_logic;
output <= my_array(sel);

This way, if sel ever becomes anything other than '0' or '1' during simulation, you will get an array index out of bounds exception. Quartus should synthesise this, Ive tested arrays using the character type as the arary index before, and it infered me a ram.