Control Of Automatic Vehicle wash m/c

Do you need an FPGA or can you fit your design in a CPLD? That's something to consider. CPLD's have some electrical advantages.

Anyway, if your going to use an FPGA, use a Cyclone III for your design. Then, using the information available on the Altera website, select a package that gives you enough user I/O and I would choose a package that supports multiple logic densities.

The idea here is to choose a package that will allow you to drop in a larger FPGA with the same footprint if you decide you need it.

Use the Quartus software to help you determine how much logic you need. If you have a partially completed design, go ahead and create a project in Quartus and compile it. You can at least get an idea of how much logic your design might take.

Ask people on the forum if they can provide examples of how much logic their designs use.

For example, I have one design that uses a Cyclone II EP2C35. It has One NIOS processor, two TSE ethernet MACs, two small TFT controllers, one DDR2 memory controller, one fairly eloborate LED controller, a UART, some PIOs, and some other miscellaneous peripherals.

That design uses ~62% of the EP2C35's logic resources.

If you're going to use any of Altera's IP cores, they always give an estimate of how many logic resources will be used.

Having those many number of io's, i don't know if a CPLD would make the cut.

but if you have no idea about how big your project is gonna be, then just jot down what kinda logic you'll be using and the components, as mentioned in the previous post. try looking for a similar system (or a system having almost similar components) and check the device they are using.

The best way to be generate the entire project on QII or Xilinx and check the fitter report on utilization... =P

i never imagined forums could be of so much help..

>>Well i will find out too but how come CPLD can be an advantage...

>>Secondly, i need help with the expansion of IOs . The FPGA do have the capacity of large no of IOs but the boards are usually not that big.

Any cost effective solution for the expansion of IOs.

>>Also the output of the sensors from the machine is 24V dc and the FPGA have all IO voltage as 3.3v. How can interface that.

As of now .. i should go with the programmin work and then find the amount of logic... then decide about the FPGA to use...

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Having those many number of io's, i don't know if a CPLD would make the cut.

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For a CPLD, both the newest MAX II family and the older MAX 3000A family have a range of package sizes and a choice of package types including some very small ones. You said you need "around 60 IOs". MAX II has a 68-pin micro FineLine BGA with 54 I/Os and a few 100-pin packages with at least 76 I/Os. MAX 3000A has 66 I/Os in a 100-pin TQFP.

If you need FPGA features like a PLL or internal RAM blocks, then Cyclone (old family, but the smallest devices might still make sense to use; 65 I/Os in a 100-pin TQFP), Cyclone II (89 I/Os in a 144-pin TQFP), and Cyclone III (newest technology; 94 I/Os in a 144-pin enhanced QFP) have fairly small package sizes.

If you care most about package size, then check the dimensions in the package data sheet for the ones that have enough I/Os. If you care most about package cost, then you'll need to ask your sales person. The package cost can be a large portion of the total device cost. A physically larger package with more I/Os of one package type might be cheaper than a physically smaller package of another package type.

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...how come CPLD can be an advantage...

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One example is that some CPLDs support a higher I/O voltage than some FPGAs (5.0V input for MAX 3000A). For the voltage you have it won't matter because you will have to use an external voltage converter for any CPLD or FPGA.

Another potential CPLD advantage is lower power dissipation. If you care about that (probably not for a washing machine), then consider MAX IIZ.

Hi,

If you are short of IO you could consider the use of I2C bus extender devices fron NXP and others. This is a 2 wire serial bus which can be controled useing the I2C bus master core from www.opencores.org (http://www.opencores.org).

Regards

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>>Also the output of the sensors from the machine is 24V dc and the FPGA have all IO voltage as 3.3v. How can interface that.

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An effective solution is using optocoupler for that signal that need to be at 24V.

To other questions, all others have just answered.