Control internal module ports during Quartus build

Hi,

I have an IP from external vendor. This IP has additional input ports which are needed and needs to be controlled in FPGA only (enabled by `ifdef FPGA). But the digital wrapper of this IP does not have these input ports. How can I control these inputs of the IP without modifying the wrapper during Quartus FPGA build (synthesis)? Can we do assign to the IP inputs during synthesis?

eg: module IP_ext (

`ifdef FPGA

input fpga_clk,

input fpga_rst,

`endif

input data_in,

output data_out

);

module wrapper (

input data_in,

output data_out

);

IP_ext u_IP_ext (

.data_in (data_in),

.data_out (data_out)

endmodule

I want to control 'fpga_clk' and 'fpga_rst' of IP_ext from the toplevel which instantiates the wrapper module while doing FPGA compilation such that these ports are connected correctly in FPGA. How can I achieve this? Note that wrapper module does not have these 2 ports and we are not supposed to edit the wrapper RTL. Kindly help.

Regards,

Suby