Honored Contributor
Honored ContributorThe receiver in an edge-aligned, source synchronous interface is responsible for phase shifting (180 degrees for SDR, 90 degrees for DDR) the incoming clock to center align it with the incoming data. TimeQuest for I/O interfaces works from the edge (the I/O) of the device. As such, in the edge-aligned case, the launch and latch edges are basically on top of each other. The FPGA with a PLL will shift the latch edge later to align it with the data.
So in the diagram you posted, picture the destination clock shifted 180 degrees to the right, keeping the red and blue arrows pointing to the same edges.
