--- Quote Start ---
Hello all!
When we have two flip flops inside the FPGA, the setup time on that path is equal to the clock period, i.e. the first flip flop launches data at 0ns, and the other should latch it at 10ns for a 100 MHz clock.
--- Quote End ---
No the setup relationship(not tSU) is 10ns, hold relationship is 0ns. The launch and latch must occur within the 10 ns window minus tSU+tH
--- Quote Start ---
In case of a single data rate source synchronous interface, when FPGA is the receiver and the transmitter is sending edge-aligned data, why is the launch edge equal to the latch edge? Why can't the transmitting flip flop send the data at 0ns, and FPGA capture it at 10 ns as in the case of an internal FPGA path?
Why do those two paths (path inside FPGA, path from tx to fpga input) have different default setup/hold relationships? Please see the below image for the default setup/hold relationship of the edge aligned source synchronous interface which I'm having difficulty understanding.
--- Quote End ---
Launch is always first then data is latched on next clock. Who says otherwise?
Honored Contributor
