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Altera_Forum's avatar
Altera_Forum
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9 years ago

continuous assignment on port list fails

Hello, Had a module with an output tied high, e.g:module a( output wire b = 1'b1); ... Quartus 16.1 synthesizes to 1'b0. Is this to be expected by the LRM? I couldn't find anyth...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I'm not sure that is valid syntax in a port declaration (continuous assignment to a wire).

This should work:

module a(

output reg b = 1'b1);

I think the issue is not that: output wire b = 1'b1 should work, but rather it should throw an error.