Constraints from LVDS blocks and logic

The message is valid for TAN and TimeQuest. The reason it makes you add them is that the destination is your own register driven by your own clock, so if you do anything "funky", you may want a different timing assignment.

I would really make sure that it's a hold issue occuring at these registers. Are you SignalTapping the capture registers(the first registers in the fabric), so you know the data at that point is incorrect? If you can do my experiment mentioned before, where the delay to these registers is longer and shorter, what happens, i.e. does getting the fitter to add delay fix everything? If you take the failing design and heat it up, does it start to work? Do the errors get worse if you cool the part down?