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Altera_Forum
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17 years ago

Constraints from LVDS blocks and logic

Hi, I have a lvds tx and rx blocks in a Stratix3. There a 20 bits with deserialisation factor of 4. With the Rx side, the data leaving the lvds is registered. The lvds and registers are using c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I have no problem using TimingQuest but at the place I work they use TAN. With my designs, I use TimingQuest but the main build of the design still used TAN. Just on a side note, MC constraints are built-in to the lvds blocks, so I don't have to add them in TimingQuest or TAN? I do remember when I selected to use an external PLL for the lvds, a message appears that I had to add constraints manually from lvds block to registers. Is this still valid or is this for TAN only?

It does look like we have a skew problem, something that doesn't appear with this design in the STX3 150 part. I've set it to run with the derive_clock_uncertainty. Not sure if there any other lvds constraints that we need to have. I've seen stuff about rskm, tccs etc. Not sure if this applies here.