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Altera_Forum
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17 years ago

Constraints from LVDS blocks and logic

Hi, I have a lvds tx and rx blocks in a Stratix3. There a 20 bits with deserialisation factor of 4. With the Rx side, the data leaving the lvds is registered. The lvds and registers are using c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

No derive_clock_uncertainty for TAN. It's only for 65nm and newer products, and I'd really, really, really, really recommend using TimeQuest. Really.