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Altera_Forum
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17 years ago

Constraints from LVDS blocks and logic

Hi, I have a lvds tx and rx blocks in a Stratix3. There a 20 bits with deserialisation factor of 4. With the Rx side, the data leaving the lvds is registered. The lvds and registers are using c...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Another thing I've noticed is that even though it says 'Multicyle-Hold Start 3' in the path summary section, it says in the waveform window of 'TimingQuest', "No Hold Multicycle Exceptions/No Exceptions" which seems to suggest that there are hold execptions despite what's in the path summary window.

I also found that if I set a multicyle hold constraint of 3 between the failing paths, it doesn't work but if I do the constrain between the two clocks, then it seems to work fine.

So, I don't know if there is something missing here regarding the hold constraint that should have been in or hasn't been picked up correctly.

MT