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Altera_Forum
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17 years ago

Constraints from LVDS blocks and logic

Hi, I have a lvds tx and rx blocks in a Stratix3. There a 20 bits with deserialisation factor of 4. With the Rx side, the data leaving the lvds is registered. The lvds and registers are using c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I've tried the all paths settings and it does work, however, when I intergrate this block into the main design (this is just a sub block in a much larger design) some of the paths fail the hold timing. So, I really need to understand this timing problem so that I can put in a fix that doesn't depend on the tools delaying the signals.

Any help would be most appreciated.

Thanks

MT