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Altera_Forum
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17 years ago

Constraints from LVDS blocks and logic

Hi, I have a lvds tx and rx blocks in a Stratix3. There a 20 bits with deserialisation factor of 4. With the Rx side, the data leaving the lvds is registered. The lvds and registers are using c...
Altera_Forum's avatar
Altera_Forum
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17 years ago

When the launch and latch clocs rise at the same time(for hold analysis), that is essentially a hold requirement of 0ns. That means your data path must be longer than your data required path, which I believe is correct. Did you re-fit after adding these constraints, or just re-run TimeQuest? Did you have Assignments -> Settings -> Fitter -> Optimize Hold Timing set to All Paths during the fit.

In this last post, are you describing the receive side or transmit side? What's your setup requirement? When you went to a hold time of 1 clock -end, did you also change your setup multicycle, since the hold requirement is dependent on the setup requirement. (I posted a document on how MCs work a while back, which might help. Let me know if you can't find it.)