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Altera_Forum
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11 years ago

Constraints for inverted clocks

The task looks simple, but I don’t know which constrain to use. I have to output two signals (200 MHz clocks) from FPGA. First is an inversion of the second: Mem_ClkP <= Clk; Mem_ClkN <=...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thank you.

But I am not designing a real device. I'm just learning constraints. Everything you suggest will work, of course, but I want to play with timequest and fitter, setting different phase deviations.

If there is no such constraint, I`ll stop thinking about that.