Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorConstraints for inverted clocks
The task looks simple, but I don’t know which constrain to use. I have to output two signals (200 MHz clocks) from FPGA. First is an inversion of the second: Mem_ClkP <= Clk; Mem_ClkN <=...
Altera_ForumHonored Contributor
Honored ContributorIf you're using an Acex, you wont be using a 200MHz clock, or constraints....
