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Altera_Forum
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11 years ago

Constraints for inverted clocks

The task looks simple, but I don’t know which constrain to use. I have to output two signals (200 MHz clocks) from FPGA. First is an inversion of the second: Mem_ClkP <= Clk; Mem_ClkN <=...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks for quick reply.

Actually, my question is not about real project. I am just learning constraints.

Pll is a good thing, but if FPGA does not have it? (Acex, for example).