Honored Contributor
Honored ContributorHi GooGooCluster
Thank you very much for your good answer. Your explanation is perfectly understandable but i have still a few questions: 1) --- Quote Start --- "how long must the launched data signal be stable (at the fpga's data output pin) before the launch clock edge (at the fpga's clock output pin)". --- Quote End --- Just about the terms: Here you speak of the launch clock. Wouldn't this rather be the latch/capture clock? And the launch clock would be the input clock of the output register inside the FPGA? 2) --- Quote Start --- In the initial case, assume that your clock and data traces just have the right length, so that the term data_trace_delay_max - clk_trace_delay_min becomes zero, and therefore max output delay = set_up_time. Makes sense, right? The launched signal must be stable before the launch clock, so that the setup time of the SDRAM register is not violated. That's no problem since you already added a 180° phase shift to the clock. --- Quote End --- So we agree that in this case the data have to be stable at the output of the fpga at least "set_up_time" before the latch/capture(in my terms) clock rises at the output of the FPGA. So why we talk about a delay equal to the setup_time? Why they don't call it an earliness or something like that? Since the Output has to be ready a specific time before the clock edge. best regards.
