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Altera_Forum
Honored Contributor
16 years agoHi wat_arg,
By default, the PLL clock name is the same as the output pin name. However, in Classic Timing Analyzer, the PLL clock name is the same as the net name. By specifying -use_tan_name option to derive_pll_clocks, you can use the net name as the PLL clock name. For example, when the instance name of the ALTPLL is inst, the c0 clock is set as follows: without -use_tan_name: inst|altpll_component|auto_generated|pll1|clk[0] with -use_tan_name: pll:inst|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]