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Altera_Forum
Honored Contributor
16 years agoHi wat_arg,
You can try the -create_base_clocks option of derive_pll_clocks. With the option, derive_pll_clocks creates the PLL input clock ('clk' in your case) if the clock is not defined. Of course you need to comment out the input clock definition. Here are the updated SDC constraints: derive_pll_clock -create_base_clocks # create_clock -period "6.666 ns" -name {clk} {clk} ;# commented out