Altera_ForumHonored Contributor11 years agoConstraining an SPI interface Hello all, What is the proper way of constraining a 4-wire SPI master interface? I have several devices connected to my SPI bus, and fastest one can accecpt a SCLK up to 33 ns period, with setu...Show More
Altera_ForumHonored Contributor11 years agoAny suggestion on how? I tried several ways but no one seems to work...
Recent DiscussionsHDMI example design errors with Agilex 7MAX10 RSU upgrade succeeds, but device boots Factory image instead of ApplicationVcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0carry chain tdcDoes the Post-Configuration BSDL Generator for Cyclone 10 LP require an NDA?