Constraining an SPI interface

Hi Dave,

Your notes are great. They helped me a lot.

There's something that I still need to understand though.

This is how the constraints look for my SPI interface:

# SPI Clocks max rate are a divided-by-4 version of system clock

create_generated_clock -name hb_spi_clk_int -source [get_pins {u0|pcie_sv_hip_avmm_0|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}] -divide_by 4 -duty_cycle 50.0 [get_pins {peanuts|peanuts_main_system0|shared_subsytem|hb_shared_spi_bus|clock_div_calc|sclk_loc|q}]

create_generated_clock -name hb_spi_clk -source [get_pins {peanuts|peanuts_main_system0|shared_subsytem|hb_shared_spi_bus|clock_div_calc|sclk_loc|q}] [get_ports {MEZZ_SER_CTRL1}] - MEZZ_SER_CTRL1 is the SPI_SCLK

# Multi-cycle relationships

set_multicycle_path -from [get_clocks {u0|pcie_sv_hip_avmm_0|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}] -to hb_spi_clk -start -hold 3

set_multicycle_path -from [get_clocks {u0|pcie_sv_hip_avmm_0|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}] -to hb_spi_clk -start -setup 2

set_multicycle_path -from hb_spi_clk -to [get_clocks {u0|pcie_sv_hip_avmm_0|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}] -end -setup 2

set_multicycle_path -from hb_spi_clk -to [get_clocks {u0|pcie_sv_hip_avmm_0|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}] -end -hold 3

# HB SPI Inputs

set_input_delay -clock hb_spi_clk -max $spi_input_delay_max [get_ports MEZZ_SER_CTRL5] - MEZZ_SER_CTRL5 is the MISO signal

set_input_delay -clock hb_spi_clk -min $spi_input_delay_min [get_ports MEZZ_SER_CTRL5]

# HB SPI Outputs

set_output_delay -clock hb_spi_clk -max $spi_output_delay_max [get_ports MEZZ_BK1_OUT14] - MEZZ_BK1_OUT14 is the SSn signal

set_output_delay -clock hb_spi_clk -min $spi_output_delay_min [get_ports MEZZ_BK1_OUT14]

set_output_delay -clock hb_spi_clk -max $spi_output_delay_max [get_ports MEZZ_BK4_OUT17] - MEZZ_BK4_OUT17 is the MOSI signal

set_output_delay -clock hb_spi_clk -min $spi_output_delay_min [get_ports MEZZ_BK4_OUT17]

TimeQuest reports that MEZZ_SER_CTRL1 port is still not fully constrained and reports a path between a spi_clk_enable signal (it gates the clock through combinatorial logic) and my core system clock (the PCI core clock, that I divide down to generate the serial clock). Attached a snapshot from the technolocy viewer.

How am I supposed to constrain that path?

Thanks