New Contributor
Super ContributorBefore diving into this in detail, is there a reason why you are not using memory IP to implement at least the PHY for this interface? You can still build your own controller if you want, but this generates the timing constraints you need on the I/O.
#iwork4intel
New ContributorAFAIK the memory controller is not compatible with LPDDR ram modules which I am using, and DDR memory in general isn't supported on cyclone 10 LP devices. The PHY isn't available in the IP library if you target a cyclone 10 LP device.
"Even though the Intel Cyclone 10 LP I/O buffers support various I/O standards for memory
application, Intel does not validate nor support any IP that is intended for memory
applications such as DDR or DDR2."
I am also generally interested in constraining two output clocks to each other, the memory controller is just the application.
