constaint timing and ouput

There is a subtlety here. Let us look at definitions of set_input_delay then that of set_output_delay.

None of them means set a specific delay as we may first think...

set_input_delay:

You are telling TimeQuest that data is offset from its arrived launching clock edge at fpga pins by min ~ max delay. i.e. TimeQuest to expect a skew of (max-min) and deal with it.

Naturally this offset is due to either external device (tCO) and/or board delays and accordingly you enter your figures.

set_output_delay:

you are telling TimeQuest to produce data offset with respect to the exiting latch clock edge but avoid any transitions from (max) before edge to (min) after edge. TimeQuest is free to produce a skew outside that timing window.

Again your figures for max/min would be derived from external board delays and external device tSU/tH requirements.

When output delay is based on tSU/tH of external device, the tool requires that tSU is entered as positive and tH as negative. This is further confusing... if you consider max is indeed max and min is indeed min relative to latch edge then min should be before max relative to edge. But SDC definition here is just weird, a common historic issue with software development.

Hence you are not really setting specific delay point from clock edge but defining the timing window that should have data settled within.

if you set both max/min to zero you are saying: timing window is zero, feel free TimeQuest. But you wouldn't get zero skew yet timing could pass !!