constaint timing and ouput

set_output_delay does not directly tell the FPGA what to do, i.e. an output -max of 5.5 and -min of 5 does not mean the data will leave between 5-5.5ns. These constraints are saying what the external device is doing. So if, for example, your clock period is 25ns, then you have a setup relationship of 25ns and hold of 0ns. If the external max delay is 5.5ns, then the FPGA has to get its data out in 25-5.5 = 19.5ns. With a hold relationship of 0ns, then the external delay of 5ns means the FPGA could get its data out as fast as -5ns and it would still meet timing. Go to www.alterawiki.com, click on Popular Pages, and around 15 is one called TimeQuest User Guide. Read through the Getting Started section, including the I/O portion.