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Altera_Forum
Honored Contributor
13 years agoI presume you are using 'multi cycle' custom instructions (possibly with a fixed cycle count of 1), rather than 'combinatorial' ones. Otherwise you don't have an 'enable' signal and clock.
To transfer data you need some latch (or fifo) to hold the data written by one cpu before being read (at a later time) by the other. For real transfer you'll need some extra control signals for flow control (etc). Not sure which part isn't working ...