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I don't know why I didn't notice it at first but there is also the option "reserve as input tri-stated with bus-hold circuitry". In that case the logic level on the unused pin is sampled at the end of configuration, and maintained during user mode. I could use this mode and connect half the unused pins to ground, and the other half to vccio, couldn't I? Or is it better to stick everything to ground and don't really care about vcc sag?
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Bus hold is useful to prevent the FPGA input buffer from floating when the pin is not driven at all external to the FPGA. However, I think it has no advantage for you over "As input tri-stated" if you are going to connect the pin externally to GND or VCC.
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Driving unused pins to GND (or VCCIO) requires definition of all connected hardware pins in the top design, even if they are yet unused.
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Setting "Reserve Pin" to "As output driving ground" for individual pins in the Assignment Editor or Pin Planner or for all unused pins in the Device and Pin Options dialog box is an alternative to having the pins in the top-level design entity. This is a way to reserve pins that are not in the design files at all. The .pin file will label these pins as "GND*", for which the .pin file says, "For non-transceiver I/O banks, connect each pin marked GND* directly to GND or leave it unconnected."
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