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Altera_Forum's avatar
Altera_Forum
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13 years ago

Connect several ALTPLL on a input port signal

Hi

I would like to connect several inputs PLL on the same input port signal. Is it possible?

The frequency input of the ALTPLL is 66MHz.

I obtain a warning

Warning: The parameters of the PLL Clk65MHz: pll1 do not have the same values - hence these PLLs cannot be merged

Info: The values of the parameter "Min Lock Period" do not match for the PLL atoms

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2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    PLLs need to be driven by dedicated clock inputs. The connection capcbilities are different for FPGA families, refer to the clock network chapter in device handbook, or ask specifically.