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Honored Contributor
Honored ContributorConnect differential input clock with the pll
How can I connect a differential clock input to the PLL?,i was trying to find a example , but they shows example using a LVDS interface, but i couldn't see how connect the differential clock input to...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Yes, I've tried , and it is, thanks Another point, if I can use the input clock as a single-ended input clock, can I use the other pin as a user I/O? thanks in advance --- Quote End --- It depends on your FPGA, you may have a look at the specifications, for example in Stratix IV, the pins I am using to send in the differential clock are defined on the data sheet as IO or optionally as dedicated clock inputs. Try to have a look at the pin out information for your FPGA, which FPGA are you using?
