Connect differential input clock with the pll

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Yes, I've tried , and it is, thanks

Another point, if I can use the input clock as a single-ended input clock, can I use the other pin as a user I/O?

thanks in advance

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It depends on your FPGA, you may have a look at the specifications, for example in Stratix IV, the pins I am using to send in the differential clock are defined on the data sheet as IO or optionally as dedicated clock inputs.

Try to have a look at the pin out information for your FPGA, which FPGA are you using?