Connect differential input clock with the pll

Hello,

since I am trying to do the same thing, I would like to make a question about the dedicated pins. I am working with a TR4 Board from Terasic, based on the Stratix IV EP4SGX530KH40C2 FPGA chip.

I am actually assigning the input of my PLL to a pin which should be appositely dedicated to a clock input (differential and configured in LVDS mode), they correspond to W35 and W34 (page3/20: http://www.altera.com/literature/dp/stratix4/ep4sgx530.pdf). This 2 pins are connected to differential clock inputs on a HSMC connector. In my design I define these pins as LVDS, and I just assign the positive one to the input of the PLL.

Everytime I compile the design, even if I have added an assignment specifying that this clock is a global signal, I get always a warning about the jitter due to non dedicated routing.

Warning (15056): PLL "PLL_Block:b1|altpll:altpll_component|PLL_Block_altpll:auto_generated|pll1" input clock inclk[0] may have reduced jitter performance because it is fed by a non-dedicated input

Info (15024): Input port INCLK[0] of node "PLL_Block:b1|altpll:altpll_component|PLL_Block_altpll:auto_generated|pll1" is driven by HSMD_CLKIN_p1~inputclkctrl which is OUTCLK output port of Clock enable block type node HSMD_CLKIN_p1~inputclkctrl

Did I maybe misunderstood the data sheet? Or is there some other step to do such as other particular assignments to force Quartus II fitting this pin with an optimized route?