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Honored Contributor
Honored ContributorConnect differential input clock with the pll
How can I connect a differential clock input to the PLL?,i was trying to find a example , but they shows example using a LVDS interface, but i couldn't see how connect the differential clock input to...
Altera_ForumHonored Contributor
Honored ContributorYes, FvM is correct. The PLL's only allow the specific clock IO's to be use with out warnings. But those clocks are capable of of differential signaling.
Make sure if you are designing your own board, and require multiple PLL's you use the correct clock input pins for different PLL's in the system. IE: Typically each pll, has 4 possible clock inputs, so ALL clock inputs can not drive ALL PLL's. (with out warnings and non-optimized skew and jitter at least). Pete
