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You should consider, that selecting individual devices in the JTAG chain for configuration involves some overhead. In my opinion, the configuration scheme
figure 9–28. jtag configuration of a single device using a microprocessor won't be well suited for this method, although it can be basically extended to a JTAG chain. I suggest to provide a JTAG chain for test and debugging purposes and use a PS or FPP configuration scheme that allows individual access to each FPGA, e.g. by using separate command and status and common DATA and DCLK lines.
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thanks FvM, you're a real altera guru.
by saying "not well suited" do you mean that this won't work properly?
by saying " it can be basically extended to a JTAG chain", do you mean that i can extend it as the figure on 9-26 ?? is this enough?
i told that this board will communicate with PC but this will be on the developer phase. later this board will be a part of a bigger standalone device and i will need to update bitstreams inside the big memory. also i will add aes encrypted communications between the main board of the standalone device and this board against chinese copies. main board will tell this board's MCU which bitstream will be configured on the fpgas.
i don't need to individual access to fpgas because all fpgas will be configured with the same bitstream.
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