Honored ContributorI ran my Cyclone 3 design with and without compressed config file
generation & in both cases the .sof file came out to be 350KB. No change with compression. Did I miss some Quartus setting or do I just have an uncompressible design ? How much compression are people seeing ?
Honored ContributorHello, FvM!
Recently I asked: --- Quote Start --- How much time will it take to load the content of EPCS4 into FPGA if payload is only ~2Mbit and the rest is filled up with 0xff ? The case is that EP4CGX22 is in "40 Mhz internal oscillator mode". There are to possible versions: 1). 4,000,000 bits x 25 ns / 1 bit = 100 ms 2). ~2,000,000 bits x 25 ns / 1 bit = ~50 ms 25 ns = 1/40MHz. Which one is correct? P.S. How to calculate decompression time by EP4CGX22? --- Quote End --- And You answered: --- Quote Start --- The latter is right, configuration bitstream load stops after the real data and a few terminating '1' s. --- Quote End --- Can You please give me any reference to Altera documents where I can find a straight-forward statement, that "configuration bitstream load stops after the real data" and the configuration time is calculated by taking into account only the "real data" ( or payload ) size of .jic file ( which can be seen in the corresponding .map file as END ADDRESS )?Honored ContributorI'm not aware of a respective statement, it's my observation, which as I assume applies to all Altera FPGA families.
If you're not sure about, you should hook up an oscilloscope or logic analyser to your development board.
