Conf_Done stays low after programming

I am trying to program an EPCS4 from an Altera USB Byteblaster, in circuit. I can program the image store, but the Cyclone II C20 device doesn't release conf_done at the end of programming although nCONFIG is going high. (This is ASP not JTAG)

What appears to be happening is that the USB-Blaster is holding the clock line low, and doesn't tri-state it after programming. The Cyclone tries to load the image but can't clock data from the EPCS4. It works fine if I manually disconnect the clock pin from the Blaster then reconnect it.

I need to keep the Blaster connected, so I'm looking at adding some electronics to disconnect the signal :-(

Didn't see this on a Byteblaster II, but I don't have one to hand to investigate. It may be that the USB blaster can sink more current, or the BBII (again Altera) might tri-state the line.

Looking at the clock line with a scope shows lots of spiky, noisy clocks with very slow rise and fall times when both devices are connected.

Anyone know of a way to make the USB Blaster release the line?

Malcolm