CONF_DONE pin not going high when trying to program Cyclone III with an SOF file

This link tells about the PLC option under convert programming files means i need to convert sof file to some other programming file before loading that image in FPGA.I tried generating a .jic file but the problem is how will the s/w tell whether it is early or late CONF_DONE assertion as the flash will load the image once we reboot the card..during which the quartus is not related to whats happening between the FPGA and the flash. or what other programming files can be generated for this debugging. I tried pof also.that dint help.