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Altera_Forum's avatar
Altera_Forum
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12 years ago

Compiling FPGAs with QSYS could be annoying. Any plan to overcome this problem?

When you generate a system with QSYS, the generator does not check the VHDL code completely. Then, when you include the generated system into your project, first you have to run the analysis and s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

If you thoroughly test every custom block separately, you only have to generate once, or at least not that often :)