Compile Error when using one inclock for SERDES IPs in different I/O banks

Hello Jens,

You might get this error because LVDS IOPLL clock is driven across multiple banks in Arria 10.

All RX channels need to be in one I/O bank and each I/O bank can support up to 24 channels for LVDS SERDES IP Core Functional Modes.

You can refer to page 4, 13, 31 and 37 document on this link: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf

I hope this answer helps.