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Altera_Forum
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17 years ago

compilation for 163 bits

hi to al! the compilation for 163 bits (2 inputs of 163 bits each and the output is also 163 bits) is not exceeding 2% of full compilation and 9% of analysis and synthesis even when the time ha...
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Altera_Forum
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17 years ago

To run a loop sequentially, that means feeding the same logic with different data, you have to use a clock and some kind of sequencer or state machine. Otherwise, the FPGA compiler is forced to calculate all iterations in parallel, which is impossible due to limited resources.